Active Low Truth Table. Q is reset to 0 by logic 0 applied to the R input. Contents show SR Latch SR latch using NOR gates SR latch.
When RESET HIGH Complement of Q1 ieQ0. E input can be considered as the control input. You can learn more about active low SR flip flops and other logic gates by checking out our full list of logic gates questions.
The above function cannot be further simplified I tried using the Karnaugh Map.
From the previous truth table it can be seen that the CLEAR CLR and PRESET inputs are active at a low logic level and put on the Q output of the Flip-Flop a high logic level regardless of the state of the clock and or the state of the J and K inputs. The SR Flip-flop Truth Table Table 521 Q output is set to logic 1 by applying logic 0 to the S input. 1239 explains the rest. That means when S00 and S1 0 the output at Y is D0 similarly Y is.
